AWRWAITUNIT=AWRWAITUNIT_0
Flash Control Register 2
| ARDSEQID | Sequence Index for AHB Read triggered Command in LUT. |
| ARDSEQNUM | Sequence Number for AHB Read triggered Command in LUT. |
| AWRSEQID | Sequence Index for AHB Write triggered Command. |
| AWRSEQNUM | Sequence Number for AHB Write triggered Command. |
| AWRWAIT | For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface |
| AWRWAITUNIT | AWRWAIT unit 0 (AWRWAITUNIT_0): The AWRWAIT unit is 2 ahb clock cycle 1 (AWRWAITUNIT_1): The AWRWAIT unit is 8 ahb clock cycle 2 (AWRWAITUNIT_2): The AWRWAIT unit is 32 ahb clock cycle 3 (AWRWAITUNIT_3): The AWRWAIT unit is 128 ahb clock cycle 4 (AWRWAITUNIT_4): The AWRWAIT unit is 512 ahb clock cycle 5 (AWRWAITUNIT_5): The AWRWAIT unit is 2048 ahb clock cycle 6 (AWRWAITUNIT_6): The AWRWAIT unit is 8192 ahb clock cycle 7 (AWRWAITUNIT_7): The AWRWAIT unit is 32768 ahb clock cycle |
| CLRINSTRPTR | Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. |